1. Field of the Invention
The present invention relates to a shift register circuit, and particularly to a shift register circuit that is formed of field-effect transistors of only the same conductivity type, for use in, e.g., a scanning line driving circuit of an image display apparatus.
2. Description of the Background Art
An image display apparatus (hereinafter “display apparatus”), such as a liquid-crystal display apparatus, has a display panel where a plurality of pixels are arranged in a matrix, and gate lines (scanning lines) are provided for individual rows of the pixels (pixel lines). The gate lines are sequentially selected and driven in cycles based on one horizontal period of the display signal, so as to update the displayed image. For the gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving the pixel lines or gate lines, a shift register that performs one cycle of shift operation in one frame period of the display signal can be used.
Preferably, such a shift register, used as a gate line driving circuit, is formed of field-effect transistors of the same conductivity type so that the display apparatus can be manufactured without requiring an increased number of process steps. Accordingly, various shift registers formed only of N-type or P-type field-effect transistors, and various display apparatuses equipped with such shift registers, have been proposed (For example, see Japanese Patent Application Laid-Open No. 2004-78172, which is hereinafter referred to as Patent Document 1). The field-effect transistors can be MOS (Metal Oxide Semiconductor) transistors or Thin-Film Transistors (TFTs), for example.
A shift register used as a gate line driving circuit is formed of a cascade connection of a plurality of shift register circuits each provided for one pixel line or one gate line. In this specification, for the sake of convenience of explanation, each of the plurality of shift register circuits of a gate line driving circuit is referred to as “a unit shift register circuit”. That is, the output terminal of each unit shift register circuit of the gate line driving circuit is connected to an input terminal of the next or following unit shift register circuit.
Patent Document 1 discloses a configuration of a conventional unit shift register circuit in FIG. 7. As shown in this diagram, the conventional unit shift register circuit includes a first transistor (M1) connected between an output terminal (GOUT[N]) and a clock terminal (CKV), and a second transistor (M2) connected between the output terminal and a first power-supply terminal (VOFF). A clock signal inputted to the clock terminal is transmitted to the output terminal, with the first transistor being on and the second transistor being off, so as to provide the output signal of the unit shift register circuit.
In particular, because the gate line driving circuit is required to rapidly charge and activate the gate lines with the output signals, the first transistor in each unit shift register circuit therein is required to offer a high driving capability (a capability of passing current). Accordingly, it is desired that the gate-source voltage of the first transistor be maintained high while the first transistor is on.
A third transistor (M3) is connected to a first node (N1) to which the gate of the first transistor is connected, so as to charge the first node. In the conventional unit shift register circuit, the third transistor is connected between the first node and a second power-supply terminal (VON), and its gate is connected to an input terminal of that unit shift register circuit (i.e., the output terminal (GOUT[N−1]) of the preceding unit shift register circuit). That is, the third transistor turns on when the output signal of the preceding unit shift register circuit is activated, and supplies charge to the first node from a power supply connected to the second power-supply terminal to charge (pre-charge) the first node. This causes the first transistor to turn on, and the clock signal which attains its H level thereafter is transmitted to the output terminal, so as to provide the output signal.
In the shift register circuit of Patent Document 1, a capacitive element (C) is connected between the first node and the output terminal, or the source of the first transistor. Accordingly, the first node is boosted by the coupling through the capacitive element when the first transistor is turned on by the pre-charging of the first node and the output terminal thereafter goes to the H level in response to the clock signal, whereby the gate-source voltage of the first transistor is kept high. As a result, the first transistor has a high driving capability.
However, while the first node is boosted, the gate-source voltage of the first transistor is not increased over the level it exhibited before being boosted, but is just kept approximately unchanged. That is, the driving capability of the first transistor of the unit shift register circuit is determined by the gate-source voltage that is given during the pre-charging by the third transistor. That is, enhancing the driving capability of the first transistor requires charging the first node to a sufficiently high level during the pre-charging.
Theoretically, when the potential at the second power-supply terminal is VDD and the threshold voltage of the third transistor is Vth, the potential at the first node is raised to VDD−Vth by the pre-charging. However, it is difficult to raise the first node to the maximum pre-charge level (VDD−Vth) when the frequency of the clock signal is high and the pulse width of the input signal (the output signal of the preceding unit shift register circuit) is narrow. One reason thereof is that the third transistor (M3) operates in a source follower mode when pre-charging the first node. That is, as the level at the first node rises, the gate-source voltage of the third transistor becomes smaller, and so the driving capability of the third transistor becomes smaller as the first node is charged, and the rate of rise of the level is therefore considerably lowered.
That is, in the conventional unit shift register circuit, the gate of the first transistor (the first node) is pre-charged by the third transistor operating in a source follower mode, and therefore charging the first node to the maximum pre-charge level takes a relatively long time. Accordingly, the first node cannot be sufficiently pre-charged when the clock signal frequency is high, which results in a reduced driving capability of the first transistor. This problem is particularly serious for the gate line driving circuit, because it has to rapidly charge and activate the gate lines with the output signals of the unit shift register circuits and therefore it requires first transistors having a high driving capability. That is, the achievement of higher resolution of the display apparatus is hindered because it is difficult to speed up the operation of the gate line driving circuit by increasing the frequency of the clock signal.